Integrated circuitry is typically fabricated on and within semiconductor substrates, such as bulk monocrystalline silicon wafers. In the context of this document, the term "semiconductor substrate" or "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Electrical components fabricated on substrates, and particularly bulk semiconductor wafers, are isolated from adjacent devices by insulating materials. One isolation technique uses trench isolation, whereby trenches are cut into a substrate and are subsequently filled with an insulating material. The insulating material is typically then planarized back to define isolated trenches filled with insulative isolation material. An example prior art construction and its associated problems are described with reference to FIG. 1. There illustrated is a semiconductor wafer fragment 10 comprising a bulk semiconductor wafer 12 having a trench isolation region 14 formed therein. A field effect transistor gate line 16 is formed over substrate 12, and conventionally comprises a gate dielectric layer, a conductively doped polysilicon region, an overlying high conductive silicide region, an insulative cap and a sidewall spacer which are not specifically designated with numerals. A source/drain diffusion region 18, also referred to as a junction, extends from proximate gate 16 to isolation trench 14.
Isolation trench 14 comprises a thermal silicon dioxide lining layer 20 and a greater volume insulating material 21 received therein. An example material 21 is undoped silicon dioxide deposited by high density plasma-enhanced decomposition of tetraethylorthosilicate (PETEOS). An insulative layer 22 is received over the substrate as illustrated. A contact opening 24 is formed through layer 22 and overlies shallow junction region 18 and shallow trench isolation region 14. In the context of this document, "shallow junction" means a depth less than or equal to about 1000 Angstroms. Unfortunately typically, material 22 also comprises an oxide material (i.e. borophosphosilicate glass) as do materials 21 and 20 within trench isolation region 14. Accordingly, typical anisotropic etching chemistries used to etch oxide insulative layer 22 also tend to etch oxide materials 20 and 21 of isolation region 14. This provides the illustrated degree of over-etch and accordingly sidewall exposure of the source/drain junction region 18. This can undesirably lead to excessive current leakage. If the contact opening etching is sufficient such that it is removed to elevationally lower than junction region 18, as shown by line 25, a fatal short to the substrate typically results.
One present prior art solution to the above problem comprises the deposition of a thin Si.sub.x N.sub.y O.sub.z layer prior to deposition of BPSG layer 22. The BPSG is then etched substantially selectively relative to the Si.sub.x N.sub.y O.sub.z layer using a contact opening mask. Then, the Si.sub.x N.sub.y O.sub.z layer is etched. Yet such Si.sub.x N.sub.y O.sub.z etching can also etch the trench oxides.
As device dimensions in integrated circuitry fabrication continue to get smaller, it is more likely that contact openings will overlie both shallow junction regions and adjacent isolation regions, thus more likely leading to contact leakage at best, and fatal substrate shorts at worst.
The invention was motivated in overcoming this particular problem, although the claims are in no way so limited, with the invention having applicability outside of its motivation in accordance with the accompanying claims as literally worded and appropriately interpreted in accordance with the Doctrine of Equivalents.